Currently, there are various processes for manufacturing a back plate of a display device, e.g., an a-Si TFT (thin film transistor) display device, a LTPS (low temperature poly-silicon) TFT display device, or an oxide TFT display device. An a-Si TFT has such drawbacks as low migration rate and poor stability, while an LTPS TFT is not adapted to the manufacture of a large-size panel. In addition, an oxide TFT usually has a depleted I-V transfer characteristic, i.e., the oxide TFT remains in an on state when its gate-to-source voltage Vgs is zero.
The depleted TFT renders a great difficulty in a design of circuits integrated in the back plate. An NAND gate is a logic circuit commonly used for digital circuits. For the two-input NAND gate, when two input signals are both at a high level, an output signal is at a low level, and when merely one input signal is at a high level and the other one is at a low level, the output signal is at a high level. As shown in FIG. 1, a commonly-used NAND gate circuit mainly consists of CMOS (complementary metal oxide semiconductor) circuits, in which two N-type TFTs for providing the input signals are connected in series and two P-type TFTs for providing the input signals are connected in parallel. In FIG. 1, A represents a first input signal, B represents a second input signal, Out represents an output signal, VDD represents a high level, and VSS represents a low level. The CMOS circuit has such advantages as small leakage current and low power consumption. For a process related to a TFT such as the oxide TFT, usually, merely one type of TFT, e.g., an N-type TFT, is used, so large leakage current and large static power consumption occur when designing a logic gate.
As shown in FIG. 2, which is a circuit diagram of the NAND gate using the N-type TFT, T1, T2 and T3 represent a first N-type TFT, a second N-type TFT and a third N-type TFT, respectively, IN1 and IN2 represent the first input signal and the second input signal, respectively, OUT represents the output signal, VDD represents the high level and VSS represents the low level. T3 works as a diode and functions as a pull-up resistor. When IN1 and IN2 are at a high level, T1 and T2 are turned on simultaneously so as to pull down OUT. However, T3 remains in the on state all the time, so there is a DC path from VDD to VSS. Meanwhile, an output low level is determined by the voltage division of series resistances between T3 and T1 as well as T2, and thus it cannot reach the low level VSS. When one or two of IN1 and IN2 are at the low level, T1 and T2 are cut off. Because T3 works as the diode, OUT is equal to VDD-VTH (a threshold voltage of T3). At this time, OUT cannot reach the high level VDD either. As mentioned above, an NAND gate of a traditional NMOS (N-metal-oxide-semiconductor) structure also has a large leakage current, and cannot be used to achieve a rail-to-rail output.